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IEICE Trans

Keyword : massively parallel computation

Hardware Architecture for Kohonen Network
Hidetoshi ONODERA Kiyoshi TAKESHITA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7 ; pp. 1159-1166
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
neural network, Kohonen network, massively parallel computation, content addressable memory, 
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