IEICE Trans

Keyword : content addressable memory

A Fast Power Estimation Method for Content Addressable Memory by Using SystemC Simulation Environment Kun-Lin TSAI I-Jui TUNG Feipei LAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/08/01 Vol. E96-A No. 8 ; pp. 1723-1729 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: content addressable memory, SystemC, power estimation, simulation,
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An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory Duc-Hung LE Katsumi INOUE Masahiro SOWA Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/10/01 Vol. E95-A No. 10 ; pp. 1708-1717 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: FPGA, information detection, content addressable memory, random access memory, parallel operation, multi-match,
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Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device Satoru HANZAWA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/08/01 Vol. E94-C No. 8 ; pp. 1302-1310 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: content addressable memory, CAM, parallel search, phase-change device, one-hot coding, nonvolatile memory,
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Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Takayuki GYOHTEN Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 ; pp. 1409-1418 Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation) Category: Keyword: content addressable memory, CAM, matrix-processing architecture, SIMD, bit-serial and word-parallel, table-lookup coding, DCT, Huffman coding, JPEG,
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Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory Seong-Ook JUNG Sei-Seung YOON
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/03/01 Vol. E91-A No. 3 ; pp. 895-898 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: content addressable memory, high speed, low power, serial CAM, parallel CAM, hybrid CAM,
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Effective Bit Selection Methods for Improving Performance of Packet Classifications on IP Routers Gang QIN Shingo ATA Ikuo OKA Chikato FUJIWARA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2007/05/01 Vol. E90-B No. 5 ; pp. 1090-1097 Type of Manuscript: PAPER Category: Switching for Communications Keyword: patricia trie, content addressable memory, quality of service, backbone router, edge router,
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Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer Takeshi KUMAKI Yasuto KURODA Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 ; pp. 334-345 Type of Manuscript: PAPER Category: Image Processing and Video Processing Keyword: content addressable memory, CAM, Huffman coding, parallel processing, pipeline, code word table,
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Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory Takeshi KUMAKI Yutaka KONO Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 ; pp. 346-354 Type of Manuscript: PAPER Category: Image Processing and Video Processing Keyword: multiport, content addressable memory, CAM, parallel processing, SIMD, categorization, bit parallel block parallel, table-lookup-coding, Huffman coding,
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Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories Yusuke OIKE Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 ; pp. 1847-1855 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: associative memory, content addressable memory, CAM, Hamming distance, capacity scalability, multi-chip structure,
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A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories Nozomu TOGAWA Takao TOTSUKA Tatsuhiko WAKUI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/05/01 Vol. E86-A No. 5 ; pp. 1082-1092 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: content addressable memory, functional memory, micro processor core, hardware/software cosynthesis, hardware/software partitioning,
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CAM Processor Synthesis Based on Behavioral Descriptions Nozomu TOGAWA Tatsuhiko WAKUI Tatsuhiko YODEN Makoto TERAJIMA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 ; pp. 2464-2473 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Co-design and High-level Synthesis Keyword: content addressable memory, functional memory, behavioral synthesis, behavioral description, high-level synthesis,
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CAM-Based Array Converter for URR Floating-Point Arithmetic Kuei-Ming LU Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/10/25 Vol. E81-D No. 10 ; pp. 1120-1130 Type of Manuscript: PAPER Category: Computer Applications Keyword: floating-point arithmetic, content addressable memory, iterative array, URR format conversion,
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CAM-Based Highly-Parallel Image Processing Hardware Takeshi OGURA Mamoru NAKANISHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 ; pp. 868-874 Type of Manuscript: INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Keyword: content addressable memory, CAM, image processing, highly-parallel processing,
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A Flexible Search Managing Circuitry for High-Density Dynamic CAMs Takeshi HAMAMOTO Tadato YAMAGATA Masaaki MIHARA Yasumitsu MURAI Toshifumi KOBAYASHI Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 ; pp. 1377-1384 Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: General Technology Keyword: content addressable memory, associative memory, dynamic memory, functional memory,
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The Trend of Functional Memory Development Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 ; pp. 1545-1554 Type of Manuscript: INVITED PAPER (Special Issue on LSI Memories) Category: Keyword: memory, functional memory, content addressable memory, associative memory, processor array,
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A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories Tadato YAMAGATA Masaaki MIHARA Takeshi HAMAMOTO Yasumitsu MURAI Toshifumi KOBAYASHI Michihiro YAMADA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 ; pp. 1657-1664 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: content addressable memory, associative memory, dynamic memory, redundancy,
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Hardware Architecture for Kohonen Network Hidetoshi ONODERA Kiyoshi TAKESHITA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 ; pp. 1159-1166 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Neural Networks and Chips Keyword: neural network, Kohonen network, massively parallel computation, content addressable memory,
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Linear Time Fault Simulation Algorithm Using a Content Addressable Memory Nagisa ISHIURA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/03/25 Vol. E75-A No. 3 ; pp. 314-320 Type of Manuscript: INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: fault simulation, content addressable memory, parallel computation,
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