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IEICE Trans

Keyword : logic block

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
Nobuaki OKADA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1437-1443
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
fine-grain reconfigurable VLSI, multiple-valued source-coupled logic, universal literal, direct allocation of CDFG, logic block, 
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