Keyword : universal literal


Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
Nobuaki OKADA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1437-1443
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
fine-grain reconfigurable VLSImultiple-valued source-coupled logicuniversal literaldirect allocation of CDFGlogic block
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Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model
Takahiro HANYU Yoshikazu YABE Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7 ; pp. 1126-1132
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Multiple-Valued Architectures and Systems
Keyword: 
resonant-tunneling diode modeluniversal literalload line methodmultiple-valued PLAwired logiccurrent-mode linear summation
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Neuron MOS Voltage-Mode Circuit Technology for Multiple-Valued Logic
Tadashi SHIBATA Tadahiro OHMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 347-356
Type of Manuscript:  INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
neuron mos transistorfunctional devicevoltage mode computationmultiple-valued logicuniversal literal
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