Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR-- Keiji KISHINENoboru ISHIHARAHaruhiko ICHINO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/04/01 Vol. E84-CNo. 4 ;
pp. 460-469 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: clock and data recovery, PLL, duplicated loop, low jitter, 2.5-Gb/s,