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| Keyword : chip-level
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Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate
Wang LIAO Masanori HASHIMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2019/04/01
Vol. E102-C
No. 4 ;
pp. 296-302
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
soft error rate, chip-level, SRAMs, flip flops, combinational circuits, | | | Summary | Full Text:PDF | |
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