Keyword : chip-level


Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate
Wang LIAO Masanori HASHIMOTO 
Publication:   
Publication Date: 2019/04/01
Vol. E102-C  No. 4 ; pp. 296-302
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
soft error ratechip-levelSRAMsflip flopscombinational circuits
 Summary | Full Text:PDF

Chip-Level Channel Estimation for the Downlink of a WCDMA System in Very High Mobility Environment
Ya-Yin YANG Jin-Fu CHANG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2009/05/01
Vol. E92-B  No. 5 ; pp. 1868-1874
Type of Manuscript:  PAPER
Category: Terrestrial Radio Communications
Keyword: 
channel estimationchip-levelhigh mobilityfast fading
 Summary | Full Text:PDF