IEICE Trans

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IEICE Trans

Keyword : cell-based design

Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation Shuichi NAGASAWA Masamitsu TANAKA Naoki TAKEUCHI Yuki YAMANASHI Shigeyuki MIYAJIMA Fumihiro CHINA Taiki YAMAE Koki YAMAZAKI Yuta SOMEI Naonori SEGA Yoshinao MIZUGAKI Hiroaki MYOREN Hirotaka TERAI Mutsuo HIDAKA Nobuyuki YOSHIKAWA Akira FUJIMAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2021/09/01 Vol. E104-C No. 9 ; pp. 435-445 Type of Manuscript: Special Section PAPER (Special Section on Fabrication of Superconductor Devices; Key Technology in Superconductor Electronics) Category: Keyword: superconducting fabrication technology, Nb/AlO_x/Nb Josephson junction, caldera planarization, multi-layer structure, single-flux quantum logic, adiabatic quantum flux parametron logic, cell-based design, diagnostic shift-registers,
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Logic Design of a Single-Flux-Quantum (SFQ) 22 Unit Switch for Banyan Networks Yoshio KAMEDA Shinichi YOROZU Shuichi TAHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/03/01 Vol. E85-C No. 3 ; pp. 625-630 Type of Manuscript: Special Section PAPER (Special Issue on Superconductive Electronics) Category: Digital Devices and Their Applications Keyword: single-flux-quantum circuit, logic design, cell-based design, deep pipeline architecture, packet switch,
	Summary \| Full Text:PDF

DEMI: A Delay Minimization Algorithm for Cell-Based Digital VLSI Design Tae Hoon KIM Young Hwan KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/03/25 Vol. E82-A No. 3 ; pp. 504-511 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: delay minimization, cell-based design, critical path analysis,
	Summary \| Full Text:PDF