IEICE Trans

Keyword : logic design

A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 ; pp. 1583-1591 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: index generation functions, linear decomposition, incompletely specified functions, balanced decision tree, content-addressable memory, logic design, heuristic,
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Circuit Description and Design Flow of Superconducting SFQ Logic Circuits Kazuyoshi TAKAGI Nobutaka KITO Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/03/01 Vol. E97-C No. 3 ; pp. 149-156 Type of Manuscript: INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits) Category: Keyword: single-flux-quantum circuit, design methodology, circuit description, logic design, layout design, design verification,
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XML Framework for Various Types of Decision Diagrams for Discrete Functions Stanislav STANKOVIC Jaakko ASTOLA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/11/01 Vol. E90-D No. 11 ; pp. 1731-1740 Type of Manuscript: PAPER Category: Contents Technology and Web Information Systems Keyword: decision diagrams, XML, graph, data structures, logic design,
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An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs Yuichi NAKAMURA Ko YOSHIKAWA Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 ; pp. 3351-3357 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic design, engineering change orders, partitioning,
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SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits Katsunori TANAKA Shigeru YAMASHITA Yahiko KAMBAYASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 ; pp. 1038-1046 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: logic design, set of pairs of functions to be distinguished (SPFD), look-up-table-based (LUT-based) field programmable gate array (FPGA), SPFD-based effective wire addition,
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Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs Hisako SATO Mariko OHTSUKA Kazuya MAKABE Yuichi KONDO Kazumasa YANAGISAWA Peter M. LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/05/01 Vol. E86-C No. 5 ; pp. 842-849 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: hot-carrier, circuit reliability, simulation, delay library, logic design,
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Logic Design of a Single-Flux-Quantum (SFQ) 22 Unit Switch for Banyan Networks Yoshio KAMEDA Shinichi YOROZU Shuichi TAHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/03/01 Vol. E85-C No. 3 ; pp. 625-630 Type of Manuscript: Special Section PAPER (Special Issue on Superconductive Electronics) Category: Digital Devices and Their Applications Keyword: single-flux-quantum circuit, logic design, cell-based design, deep pipeline architecture, packet switch,
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Design of Multiple-Valued Programmable Logic Array with Unary Function Generators Yutaka HATA Naotake KAMIURA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/09/25 Vol. E82-D No. 9 ; pp. 1254-1260 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, programmable logic array, unary function, logic design, minimization,
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Efficient Triadic Generators for Logic Circuits Grant POGOSYAN Takashi NAKAMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/05/25 Vol. E82-D No. 5 ; pp. 919-924 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications) Category: Logic and Logic Functions Keyword: multi-valued logic, logic design, generating sets,
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Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate Xiaowei DENG Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/08/25 Vol. E78-D No. 8 ; pp. 951-958 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, super pass gate, logic design, quantum devices, super pass transistor model,
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Lower Bounds on Size of Periodic Functions in Exclusive-OR Sum-of-Products Expressions Yasuaki NISHITANI Kensuke SHIMIZU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/03/25 Vol. E77-A No. 3 ; pp. 475-482 Type of Manuscript: Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems) Category: Computer Aided Design (CAD) Keyword: exclusive-OR sum-of-products, size of circuits, lower bound, logic minimization, logic design,
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