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IEICE Trans

Keyword : built-in soft error

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 340-346
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
TMR, built-in soft error, SEU, SET, 
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