IEICE Trans - An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity

Jun FURUTA
Kazutoshi KOBAYASHI
Hidetoshi ONODERA

Publication
IEICE TRANSACTIONS on Electronics Vol.E93-C No.3 pp.340-346
Publication Date: 2010/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.340
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category:
Keyword:
TMR, built-in soft error, SEU, SET,

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Summary:
According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a "BISER" (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.