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IEICE Trans

Keyword : STT-MRAM

Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme
Ziyue ZHANG Takashi OHSAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2020/08/01
Vol. E103-C  No. 8 ; pp. 372-380
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
dummy cell average read scheme, CBLSA, STT-MRAM, array design, high access speed, 
 Summary | Full Text:PDF
Time Dependent Percolation Analysis of the Degradation of Coherent Tunneling in Ultra-Thin CoFeB/MgO/CoFeB Magnetic Tunneling Junctions
Keiji HOSOTANI Makoto NAGAMINE Ryu HASUNUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2020/05/01
Vol. E103-C  No. 5 ; pp. 254-262
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
STT-MRAM, MgO, TDDB, percolation, 
 Summary | Full Text:PDF
A New Read Scheme for High-Density Emerging Memories
Takashi OHSAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2018/06/01
Vol. E101-C  No. 6 ; pp. 423-429
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ReRAM, STT-MRAM, PCRAM, memristor, reference cell, dummy cell, redundancy, bit yield, weighted average, 
 Summary | Full Text:PDF
STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier
Yohei UMEKI Koji YANAGIDA Shusuke YOSHIMOTO Shintaro IZUMI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI Koji TSUNODA Toshihiro SUGII 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2411-2417
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
STT-MRAM, low-voltage, process-variation-tolerant, 
 Summary | Full Text:PDF
Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits
Jisu KIM Jee-Hwan SONG Seung-Hyuk KANG Sei-Seung YOON Seong-Ook JUNG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6 ; pp. 912-921
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
STT-MRAM, sensing circuit, sensing margin, load-line analysis, read disturbance, 
 Summary | Full Text:PDF