A New Read Scheme for High-Density Emerging Memories

Takashi OHSAWA  

IEICE TRANSACTIONS on Electronics   Vol.E101-C   No.6   pp.423-429
Publication Date: 2018/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E101.C.423
Type of Manuscript: PAPER
Category: Electronic Circuits
ReRAM,  STT-MRAM,  PCRAM,  memristor,  reference cell,  dummy cell,  redundancy,  bit yield,  weighted average,  

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Several new memories are being studied as candidates of future DRAM that seems difficult to be scaled. However, the read signal in these new memories needs to be amplified in a single-end manner with reference signal supplied if they are aimed for being applied to the high-density main memory. This scheme, which is fortunately not necessary in DRAM's 1/2Vdd pre-charge sense amp, can become a serious bottleneck in the new memory development, because the device electrical parameters in these new memory cells are prone to large cell-to-cell variations without exception. Furthermore, the extent to which the parameter fluctuates in data “1” is generally not the same as in data “0”. In these situations, a new sensing scheme is proposed that can minimize the sensing error rate for high-density single-end emerging memories like STT-MRAM, ReRAM and PCRAM. The scheme is based on averaging multiple dummy cell pairs that are written “1” and “0” in a weighted manner according to the fluctuation unbalance between “1” and “0”. A detailed analysis shows that this scheme is effective in designing 128Mb 1T1MTJ STT-MRAM with the results that the required TMR ratio of an MTJ can be relaxed from 130% to 90% for the fluctuation of 6% sigma-to-average ratio of MTJ resistance in a 16 pair-dummy cell averaging case by using this technology when compared with the arithmetic averaging method.