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| Keyword : HDL
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Asynchronous Circuit Design on Field Programmable Gate Array Devices
Jung-Lin YANG Shin-Nung LU Pei-Hsuan YU | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C
No. 4 ;
pp. 516-522
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
asynchronous, bundled-data, burst-mode, extended burst-mode, FPGA, generalized C-element, HDL, self-timed, | | | Summary | Full Text:PDF | |
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New Trend and Future Issues of Hardware Description Language and High-Level Synthesis
Masaharu IMAI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A
No. 3 ;
pp. 307-313
Type of Manuscript:
INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
HDL, high-level synthesis, VHDL, verilog HDL, UDL/I, PARTHENON, SFL, | | | Summary | Full Text:PDF | |
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