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CMOS Circuit Simulation Using Latency Insertion Method
Tadatoshi SEKINE Hideki ASAI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A
No. 10 ;
pp. 2546-2553
Type of Manuscript:
Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Problems
Keyword:
latency insertion method, CMOS circuit, fast circuit simulation, | | | Summary | Full Text:PDF | |
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Comprehensive Matching Characterization of Analog CMOS Circuits
Hiroo MASUDA Takeshi KIDA Shin-ichi OHKAWA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A
No. 4 ;
pp. 966-975
Type of Manuscript:
Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
mismatch, small signal parameter, CMOS circuit, analog, | | | Summary | Full Text:PDF | |
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Stuck–Open Fault Detection in CMOS Circuits Using Single Test Patterns
Enrico MACII Qing XU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A
No. 11 ;
pp. 1977-1979
Type of Manuscript:
LETTER
Category: Computer Aided Design (CAD)
Keyword:
CMOS circuit, stuck–open fault, test generation, | | | Summary | Full Text:PDF | |
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54 CMOS Redundant Binary Parallel Multiplier