Keyword : CMOS circuit


CMOS Circuit Simulation Using Latency Insertion Method
Tadatoshi SEKINE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A  No. 10 ; pp. 2546-2553
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Problems
Keyword: 
latency insertion methodCMOS circuitfast circuit simulation
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A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique
Xian Ping FAN Pak Kwong CHAN Piew Yoong CHEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5 ; pp. 719-727
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
analog-to-digital converter (ADC)subranging ADCpipeline schemeCMOS integrated circuitswitched-capacitor circuitCMOS circuit
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Comprehensive Matching Characterization of Analog CMOS Circuits
Hiroo MASUDA Takeshi KIDA Shin-ichi OHKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 966-975
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
mismatchsmall signal parameterCMOS circuitanalog
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Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model
Yukiya MIURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1551-1557
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Analog/Mixed Signal Test
Keyword: 
abstract circuit modelanalog and mixed-signal circuitsanalysis and testingCMOS circuitoperation region
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A Compact Radix-64 54 54 CMOS Redundant Binary Parallel Multiplier
Sang-Hoon LEE Seung-Jun BAE Hong-June PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/06/01
Vol. E85-C  No. 6 ; pp. 1342-1350
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
parallel multiplierredundant binaryradix-64CMOS circuitdigital circuit
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Power Estimation and Reduction of CMOS Circuits Considering Gate Delay
Hiroaki UEDA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/01/25
Vol. E82-D  No. 1 ; pp. 301-308
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
CMOS circuitlow power designgate delaytransition probabilityswitching activity
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A Design of High-Speed 4-2 Compressor for Fast Multiplier
Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Hirofumi SHINOHARA Koichiro MASHIKO Tadashi SUMI Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4 ; pp. 538-548
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
4-2 compressormultiplierredundant binarytransmission gateCMOS circuit
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Stuck–Open Fault Detection in CMOS Circuits Using Single Test Patterns
Enrico MACII Qing XU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1977-1979
Type of Manuscript:  LETTER
Category: Computer Aided Design (CAD)
Keyword: 
CMOS circuitstuck–open faulttest generation
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