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IEICE Trans

Keyword : packet-reordering circuit

Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
Yuta UKON Koji YAMAZAKI Koyo NITTA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2020/01/01
Vol. E103-B  No. 1 ; pp. 11-19
Type of Manuscript:  Special Section PAPER (Special Section on Internet Architecture, Applications and Operation Technologies for a Cyber-Physical System)
Category: Network System
Keyword: 
service function chaining, real-time image processing, packet-reordering circuit, CPU-FPGA architecture, 
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