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IEICE Trans

Keyword : wire sizing

Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis
Takashi ENAMI Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2261-2271
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
power distribution network, decoupling capacitance, timing analysis, statistical static timing analysis, decap insertion, wire sizing, 
 Summary | Full Text:PDF
A Performance-Driven Floorplanning Method with Interconnect Performance Estimation
Shinya YAMASAKI Shingo NAKAYA Shin'ichi WAKABAYASHI Tetsushi KOIDE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2775-2784
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
floorplanning, timing-driven layout, buffer insertion, wire sizing, simulated annealing, 
 Summary | Full Text:PDF
A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design
Kwang-Ki RYOO Hyunchul SHIN Jong-Wha CHONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1115-1122
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
clock routing, bounded skew, topology, wire sizing, 
 Summary | Full Text:PDF