A Performance-Driven Floorplanning Method with Interconnect Performance Estimation

Shinya YAMASAKI  Shingo NAKAYA  Shin'ichi WAKABAYASHI  Tetsushi KOIDE  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E85-A   No.12   pp.2775-2784
Publication Date: 2002/12/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
floorplanning,  timing-driven layout,  buffer insertion,  wire sizing,  simulated annealing,  

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Summary: 
In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.