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IEICE Trans

Keyword : timing-driven layout

A Performance-Driven Floorplanning Method with Interconnect Performance Estimation
Shinya YAMASAKI Shingo NAKAYA Shin'ichi WAKABAYASHI Tetsushi KOIDE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2775-2784
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
floorplanning, timing-driven layout, buffer insertion, wire sizing, simulated annealing, 
 Summary | Full Text:PDF