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IEICE Trans

Keyword : switching activity reduction

On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating
Yu JIN Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2191-2198
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
dynamic power reduction, switching activity reduction, controlling value-based power controlling, BDD, 
 Summary | Full Text:PDF