Yu JIN


Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization
Yu JIN Zhe DU Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2568-2575
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
pseudo power gatinglow power combinational circuitgate level power optimization
 Summary | Full Text:PDF

On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating
Yu JIN Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2191-2198
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
dynamic power reductionswitching activity reductioncontrolling value-based power controllingBDD
 Summary | Full Text:PDF