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IEICE Trans

Keyword : resource binding

Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches
Keisuke INOUE Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/08/01
Vol. E96-A  No. 8 ; pp. 1712-1722
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
flip-flop/latch-based design, high-level synthesis, resource binding, storage-type selection, 
 Summary | Full Text:PDF
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
Juinn-Dar HUANG Chia-I CHEN Wan-Ling HSU Yen-Ting LIN Jing-Yang JOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/02/01
Vol. E95-A  No. 2 ; pp. 559-566
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Behavioral synthesis, distributed register-file, performance optimization, low-power, resource binding, scheduling, 
 Summary | Full Text:PDF
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
Juinn-Dar HUANG Chia-I CHEN Yen-Ting LIN Wan-Ling HSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/04/01
Vol. E94-A  No. 4 ; pp. 1151-1155
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
communication synthesis, distributed register-file microarchitecture, interconnect minimization, resource binding, scheduling, 
 Summary | Full Text:PDF
A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration
Nozomu TOGAWA Takafumi HISAKI Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2563-2575
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-level Synthesis
Keyword: 
data-flow oriented process, high-level synthesis, data-flow graph enumeration, scheduling, resource binding, 
 Summary | Full Text:PDF
A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis
Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6 ; pp. 1231-1241
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
scheduling, resource binding, high-level synthesis, data-flow graph, gradual time-frame reduction, 
 Summary | Full Text:PDF