A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework Yukihide KOHIRAAtsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/10/01 Vol. E91-ANo. 10 ;
pp. 3030-3037 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: register relocation, retiming, clock scheduling, general-synchronous framework,
Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization Yukihide KOHIRAAtsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-ANo. 4 ;
pp. 800-807 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: register relocation, retiming, clock period minimization, generalized synchronous framework,