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IEICE Trans

Keyword : placement optimization

Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits
Pei-Wen LUO Jwu-E CHEN Chin-Long WEY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/01/01
Vol. E94-A  No. 1 ; pp. 352-361
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
yield enhancement, mismatch, common centroid, spatial correlation, process variation, placement optimization, 
 Summary | Full Text:PDF
WSSA: A High Performance Simulated Annealing and Its Application to Transistor Placement
Shunji SAIKA Masahiro FUKUI Masahiko TOYONAGA Toshiro AKINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2584-2591
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Synthesis
Keyword: 
simulated annealing, temperature scheduling, phase transition, placement optimization, cell synthesis, 
 Summary | Full Text:PDF