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IEICE Trans

Keyword : pipeline processing

Small-Area CNN Inference Architecture with Bit-Serial Pipeline Datapath and Zero Skipping
Shinya HATTORI Hiroyuki OCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2026/03/01
Vol. E109-A  No. 3 ; pp. 552-562
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
bit-serial arithmetic unit, pipeline processing, convolutional neural network, rectified linear unit, high-performance, and area-efficient, 
 Summary | Full Text:PDF
An Efficient Implementation Method of a Metric Computation Accelerator for Fractal Image Compression Using Reconfigurable Hardware
Hidehisa NAGANO Akihiro MATSUURA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/01/01
Vol. E84-A  No. 1 ; pp. 372-377
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
fractal image compression, metric computation, reconfigurable hardware, pipeline processing, 
 Summary | Full Text:PDF
Fast Implementation Technique for Improving Throughput of RLS Adaptive Filters
Kiyoshi NISHIKAWA Hitoshi KIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A  No. 8 ; pp. 1545-1550
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Adaptive Signal Processing
Keyword: 
adaptive system, pipeline processing, digital signal processor, RLS adaptive filters, 
 Summary | Full Text:PDF
A Pipelined Architecture for Normalized LMS Adaptive Digital Filters
Akio HARADA Kiyoshi NISHIKAWA Hitoshi KIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2 ; pp. 223-229
Type of Manuscript:  Special Section PAPER (Special Section on VLSI for Digital Signal Processing)
Category: 
Keyword: 
adaptive digital filter, pipeline processing, normalized LMS algorithm, 
 Summary | Full Text:PDF
A Fault Tolerant Intercommunication Scheme Using Bank Memory Switching
Norihiko TANAKA Takakazu KUROKAWA Takashi MATSUBARA Yoshiaki KOGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6 ; pp. 804-809
Type of Manuscript:  Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
fault tolerance, multi-processor intercommunication, bank memory switching, pipeline processing, ring network, 
 Summary | Full Text:PDF