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IEICE Trans

Keyword : lock-in range

All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter
Mitsutoshi YAHARA Kuniaki FUJIMOTO Hirofumi SASAKI Takashi SHIBUYA Yoshinori HIGASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A  No. 6 ; pp. 1527-1532
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: 
Keyword: 
PLL, jitter, delay clock, lock-in range, digital, 
 Summary | Full Text:PDF