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IEICE Trans

Keyword : interconnects

Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA
Yuya MATSUMOTO Yuichi TANJI Mamoru TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/01/01
Vol. E87-A  No. 1 ; pp. 251-257
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
signal integrity, interconnects, passive reduced-order models, PRIMA, SPICE, 
 Summary | Full Text:PDF