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IEICE Trans

Keyword : interconnect minimization

Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
Juinn-Dar HUANG Chia-I CHEN Yen-Ting LIN Wan-Ling HSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/04/01
Vol. E94-A  No. 4 ; pp. 1151-1155
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
communication synthesis, distributed register-file microarchitecture, interconnect minimization, resource binding, scheduling, 
 Summary | Full Text:PDF
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
Ya-Shih HUANG Yu-Ju HONG Juinn-Dar HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3143-3150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
multicycle communication, communication synthesis, interconnect minimization, resource allocation, resource sharing, scheduling, routing, 
 Summary | Full Text:PDF