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Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
Ya-Shih HUANG Yu-Ju HONG Juinn-Dar HUANG
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E92-A
No.12
pp.3143-3150 Publication Date: 2009/12/01 Online ISSN: 1745-1337
DOI: 10.1587/transfun.E92.A.3143 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: multicycle communication, communication synthesis, interconnect minimization, resource allocation, resource sharing, scheduling, routing,
Full Text: PDF>>
Summary:
In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.
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