Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-ANo. 6 ;
pp. 1464-1475 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: software pipelining, interconnect delay, high level synthesis, scheduling, performance,
Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect Yasuhiro OGASAHARAMasanori HASHIMOTOTakao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-ANo. 4 ;
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