Kenshu SETO


Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
Shanghua GAO Hiroaki YOSHIDA Kenshu SETO Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6  pp. 1464-1475
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
software pipelininginterconnect delayhigh level synthesisschedulingperformance
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