Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization Yukihide KOHIRAAtsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-ANo. 4 ;
pp. 800-807 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: register relocation, retiming, clock period minimization, generalized synchronous framework,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-ANo. 4 ;
pp. 892-898 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: delay insertion, clock period minimization, semi-synchronous circuit, delay-slack, delay-demand,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-ANo. 11 ;
pp. 2383-2389 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: delay insertion, clock period minimization, semi-synchronous circuit,