Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A
No. 6 ;
pp. 904-910
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Parallel Processor Scheduling
Keyword:
minimum-latency architecture, special-purpose VLSI processor, parallel processing, communication time, bus interconnection network, |