Keyword : bus interconnection network


Unified Scheduling of High Performance Parallel VLSI Processors for Robotics
Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6 ; pp. 904-910
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Parallel Processor Scheduling
Keyword: 
minimum-latency architecturespecial-purpose VLSI processorparallel processingcommunication timebus interconnection network
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