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IEICE Trans

Keyword : behavioral model

Determining Memory Polynomial Model Parameters from Those of Complex p-th Order Inverse for Designing Predistorter
Michiharu NAKAMURA Eisuke FUKUDA Yoshimasa DAIDO Keiichi MIZUTANI Takeshi MATSUMURA Hiroshi HARADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2021/11/01
Vol. E104-B  No. 11 ; pp. 1429-1440
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
behavioral model, memory polynomial, digital predistorter (DPD), non-linear power amplifier, linearlizer, 
 Summary | Full Text:PDF
A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design
Zule XU Takayuki KAWAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2017/04/01
Vol. E100-C  No. 4 ; pp. 370-372
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
ring oscillator, phase-locked loop, behavioral model, digital PLL, 
 Summary | Full Text:PDF
An Automatic Integrator Macromodel Generation Method for Behavioral Simulation of SC Sigma-Delta Modulators
Ailin ZHANG Guoyong SHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/05/01
Vol. E99-A  No. 5 ; pp. 908-916
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
automatic model generation, behavioral model, operational amplifier (opamp), switched-capacitor (SC) integrator, Sigma-Delta modulator (SDM), 
 Summary | Full Text:PDF
Yield-Ensuring DAC-Embedded Opamp Design Based on Accurate Behavioral Model Development
Yeong-Shin JANG Hoai-Nam NGUYEN Seung-Tak RYU Sang-Gug LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6 ; pp. 935-937
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
DAC, DAC-embedded, behavioral model, yield, 
 Summary | Full Text:PDF
A Practical Method for System-Level Bus Architecture Validation
Kazuyoshi TAKEMURA Masanobu MIZUNO Akira MOTOHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2439-2445
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Methodology
Keyword: 
system-level design, bus architecture validation, bus-cycle-accurate, behavioral model, interface model, 
 Summary | Full Text:PDF