Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-ANo. 12 ;
pp. 2439-2445 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Methodology Keyword: system-level design, bus architecture validation, bus-cycle-accurate, behavioral model, interface model,
