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IEICE Trans

Keyword : array multipliers

A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers
Takahiro YAMAMOTO Ittetsu TANIGUCHI Hiroyuki TOMIYAMA Shigeru YAMASHITA Yuko HARA-AZUMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1496-1499
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
approximate computing, array multipliers, SMT solver, 
 Summary | Full Text:PDF