For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers
Takahiro YAMAMOTO Ittetsu TANIGUCHI Hiroyuki TOMIYAMA Shigeru YAMASHITA Yuko HARA-AZUMI
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2017/07/01
Online ISSN: 1745-1337
Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
approximate computing, array multipliers, SMT solver,
Full Text: PDF>>
Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.