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| Keyword : VLSI layout
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VLSI Layout of Trees into Grids of Minimum Width
Akira MATSUBAYASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/05/01
Vol. E87-A
No. 5 ;
pp. 1059-1069
Type of Manuscript:
Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category:
Keyword:
VLSI layout, graph layout, graph embedding, grid, aspect ratio, | | | Summary | Full Text:PDF | |
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On the Complexity of Minimum Congestion Embedding of Acyclic Graphs into Ladders
Akira MATSUBAYASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/05/01
Vol. E84-A
No. 5 ;
pp. 1218-1226
Type of Manuscript:
Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category:
Keyword:
graph embedding, graph layout, VLSI layout, grid, | | | Summary | Full Text:PDF | |
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The Complexity of Embedding of Acyclic Graphs into Grids with Minimum Congestion
Akira MATSUBAYASHI Masaya YOKOTA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/11/25
Vol. E83-A
No. 11 ;
pp. 2390-2394
Type of Manuscript:
LETTER
Category: Graphs and Networks
Keyword:
graph embedding, graph layout, VLSI layout, grid, | | | Summary | Full Text:PDF | |
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On the Complexity of Embedding of Graphs into Grids with Minimum Congestion
Akira MATSUBAYASHI Shuichi UENO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/04/25
Vol. E79-A
No. 4 ;
pp. 469-476
Type of Manuscript:
Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category:
Keyword:
NP-completeness, graph embedding, congestion, grid, VLSI layout, | | | Summary | Full Text:PDF | |
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