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| Keyword : SFL
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Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser
Naohiko SHIMIZU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A
No. 12 ;
pp. 3225-3229
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Methodology
Keyword:
logic synthesis, HDL conversion, SFL, verilog, | | | Summary | Full Text:PDF | |
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New Trend and Future Issues of Hardware Description Language and High-Level Synthesis
Masaharu IMAI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A
No. 3 ;
pp. 307-313
Type of Manuscript:
INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
HDL, high-level synthesis, VHDL, verilog HDL, UDL/I, PARTHENON, SFL, | | | Summary | Full Text:PDF | |
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