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IEICE Trans

Keyword : HW/SW co-design

Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
Shinsuke KOBAYASHI Yoshinori TAKEUCHI Akira KITAJIMA Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3 ; pp. 748-754
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
multi-threading, very long instruction word (VLIW), instruction level parallelism, thread level parallelism, HW/SW co-design, 
 Summary | Full Text:PDF
A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency
Katsuya SHINOHARA Norimasa OHTSUKI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2356-2365
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
performance optimization, clock frequency tuning, pipelined ASIPs, HW/SW co-design, 
 Summary | Full Text:PDF
Polling-Based Real-Time Software for MPEG2 System Protocol LSIs
Jiro NAGANUMA Makoto ENDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 695-701
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
MPEG2, protocol processing, multiplexer/demultiplexer, real-time software, embedded system, HW/SW co-design, VLSI, 
 Summary | Full Text:PDF