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| Yuichi NAKAMURA
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A Verification and Analysis Tool Set for Embedded System Design
Yuichi NAKAMURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12
pp. 2788-2793
Type of Manuscript:
INVITED PAPER (Special Section on Mathematical Systems Science and its Applications)
Category:
Keyword:
embedded systems, verification, | | | Summary | Full Text:PDF | |
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Fast FPGA-Emulation-Based Simulation Environment for Custom Processors
Yuichi NAKAMURA Kouhei HOSOKAWA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A
No. 12
pp. 3464-3470
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword:
custom processor, simulation, emulation, FPGA, | | | Summary | Full Text:PDF | |
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Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs
Yuichi NAKAMURA Takeshi YOSHIMURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A
No. 12
pp. 3458-3463
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword:
SoC, power consumption, power estimation, toggle rate, | | | Summary | Full Text:PDF | |
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An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs
Yuichi NAKAMURA Ko YOSHIKAWA Takeshi YOSHIMURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A
No. 12
pp. 3351-3357
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
logic design, engineering change orders, partitioning, | | | Summary | Full Text:PDF | |
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