Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization Yu JINZhe DUShinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-ANo. 12pp. 2568-2575 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: pseudo power gating, low power combinational circuit, gate level power optimization,
On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating Yu JINShinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-ANo. 12pp. 2191-2198 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: dynamic power reduction, switching activity reduction, controlling value-based power controlling, BDD,