IEICE Trans

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IEICE Trans

Yoshihiro HAYASHI

Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation Noriaki ODA Hironori IMURA Naoyoshi KAWAHARA Masayoshi TAGAMI Hiroyuki KUNISHIMA Shuji SONE Sadayuki OHNISHI Kenta YAMADA Yumi KAKUHARA Makoto SEKINE Yoshihiro HAYASHI Kazuyoshi UENO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 848-855 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Device Keyword: copper, low-k, CMOS, interconnect, design, application,
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7-Mask Self-Aligned SiGe Base Bipolar Transistors with f_T of 80 GHz Tsutomu TASHIRO Takasuke HASHIMOTO Fumihiko SATO Yoshihiro HAYASHI Toru TATSUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/05/25 Vol. E80-C No. 5 pp. 707-713 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: bipolar transistor, silicon-germanium base, selective epitaxial growth, CMP, trench isolation, f_T,
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A 1.55 µm, 450 Mbit/s High-Sensitivity Receiver Design and a Long Distance Transmission Experiment Yukio KOBAYASHI Yoshihiro HAYASHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/05/25 Vol. E70-E No. 5 pp. 460-466 Type of Manuscript: PAPER Category: Communication Systems and Communication Protocols Keyword:
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