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On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques
Chia-Yi LIN Li-Chung HSU Hung-Ming CHEN | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C
No. 3
pp. 369-378
Type of Manuscript:
Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category:
Keyword:
DFT, TSP, test power, | | | Summary | Full Text:PDF | |
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A 2 V 2.4 GHz Fully Integrated CMOS LNA with Q-Enhancement Circuit for SOC Design
Chih-Lung HSIAO Ro-Min WENG Kun-Yi LIN | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2003/06/01
Vol. E86-C
No. 6
pp. 1050-1055
Type of Manuscript:
Special Section PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems)
Category:
Keyword:
LNA,CMOS,SOC,RF IC, | | | Summary | Full Text:PDF | |
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