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IEICE Trans

Xin MAN

Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8  pp. 1347-1358
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
actual power reduction, automatic multi-stage clock gating optimization, ILP formulation, switching activity, BDD, MIP optimizer, 
 Summary | Full Text:PDF
Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2472-2480
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
automatic clock gating generation, low power, dynamic power reduction, BDD, 
 Summary | Full Text:PDF