Keyword : dynamic power reduction

On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating
Yu JIN Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2191-2198
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
dynamic power reduction, switching activity reduction, controlling value-based power controlling, BDD, 
 Summary | Full Text:PDF
Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2472-2480
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
automatic clock gating generation, low power, dynamic power reduction, BDD, 
 Summary | Full Text:PDF
Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity
Lei CHEN Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3111-3118
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
power gating, multi-threshold CMOS (MTCMOS), controlling value, dynamic power reduction, maximum depth constraint, CV-based power gating, 
 Summary | Full Text:PDF
CKVdd: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits
Ching-Hwa CHENG Chin-Hsien WANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 391-400
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
dynamic power reduction, ramp voltage, power switch, 
 Summary | Full Text:PDF
Leakage Power Reduction for Battery-Operated Portable Systems
Yun CAO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3200-3203
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Power Optimization
Keyword: 
bitwidth optimization, leakage power reduction, dynamic power reduction, 
 Summary | Full Text:PDF