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IEICE Trans

Toru NOJIRI

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation
Yoshitaka HIRAMATSU Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Toru NOJIRI Kunio UCHIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/12/01
Vol. E95-C  No. 12  pp. 1872-1882
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
block matching, heterogeneous multi-core, dynamically reconfigurable processor, data transfer, accelerator, 
 Summary | Full Text:PDF