Keyword : dynamically reconfigurable processor


Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation
Yoshitaka HIRAMATSU Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Toru NOJIRI Kunio UCHIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/12/01
Vol. E95-C  No. 12 ; pp. 1872-1882
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
block matchingheterogeneous multi-coredynamically reconfigurable processordata transferaccelerator
 Summary | Full Text:PDF

Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor
Takao TOI Takumi OKAMOTO Toru AWASHIMA Kazutoshi WAKABAYASHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2619-2627
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
coarse-grained reconfigurable architecturedynamically reconfigurable processorhigh-level synthesisiterative synthesiswire delay
 Summary | Full Text:PDF

Resource Minimization Method Satisfying Delay Constraint for Replicating Large Contents
Sho SHIMIZU Hiroyuki ISHIKAWA Yutaka ARAKAWA Naoaki YAMANAKA Kosuke SHIBA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2009/10/01
Vol. E92-B  No. 10 ; pp. 3102-3110
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
content delivery networkreplica placementdynamically reconfigurable processorexhaustive search
 Summary | Full Text:PDF

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors
Vu Manh TUAN Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/12/01
Vol. E91-D  No. 12 ; pp. 2793-2803
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
dynamically reconfigurable processorpreemption algorithmpreemption latencyhardware overhead
 Summary | Full Text:PDF

A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors
Vu MANH TUAN Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/09/01
Vol. E91-D  No. 9 ; pp. 2312-2322
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
dynamically reconfigurable processormulti-process executionsingle-process execution
 Summary | Full Text:PDF

Dynamically Reconfigurable Processor Implemented with IPFlex's DAPDNA Technology
Takayuki SUGAWARA Keisuke IDE Tomoyoshi SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/08/01
Vol. E87-D  No. 8 ; pp. 1997-2003
Type of Manuscript:  INVITED PAPER (Special Section on Reconfigurable Systems)
Category: 
Keyword: 
dynamically reconfigurable processorcoarse-grain processing elementheterogeneous two-dimensional arrayspatial computingtemporal computing
 Summary | Full Text:PDF